1. Field of the Invention
Embodiments of the invention relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for maskless formation of patterned areas on a substrate.
2. Discussion of Related Art
Modern devices, such as semiconductor chips, microelectromechanical (MEMS), magnetic storage devices, and solar cells are typically fabricated using complex patterning processes such as photolithography. In the field of solar cells, an interdigitated back contact (IBC) solar cell shows promise due to the high efficiency that is rendered possible by placement of electrodes on the back surface of the device so that no light for producing electric current is blocked. Commercial examples of such cells include heterojunction IBC cells offered by Sanyo corporation and homojunction IBC cells offered by SunPower Corporation. Although IBC cells may provide high efficiency, the number of manufacturing steps and costs associated with each step contribute to comparatively higher costs to manufacture. In addition, these steps also contribute to a low throughput, meaning the overall amount of IBC cells that can be manufactured in a given time period. Some of the factors that contribute to the higher costs and lower throughput include: a) two lithographic patterning steps, which add considerable expense due to the inherent complexity of photolithographic tools and related processes; b) costs of consumables used in conjunction with lithography (photoresist, developers, hardmasks, etch, strip, etc.); and c) metallization processes, including plating materials and tooling.
FIG. 1 illustrates one prior art conventional method for forming a heterojunction IBC cell. This conventional method requires the formation of alternate, patterned stacked dielectric layers consisting of intrinsic amorphous silicon (a-Si) and doped amorphous silicon. An interdigitated layout having alternate p-type and n-type doped structures may be formed by the process illustrated. Other layouts may have more complex p-type and n-type structures. At step 90, an n-type substrate is selected and texturing of the substrate takes place using KOH at step 92. At step 94, chemical oxide is grown on the substrate. At step 96, intrinsic amorphous silicon is grown on both sides of a wafer. At step 98, a nitride antireflective coating is grown. At step 102, P-doped amorphous silicon is grown on the back side. At step 104, a lithography coating process takes place to pattern the p-doped layer. At step 106, a plasma etch takes place to etch out regions of the P-doped layer. At step 108, resist is removed. At step 110, a thin layer of intrinsic amorphous silicon is deposited, followed by a thicker layer of N+ doped amorphous silicon on the back side. The N+ doped amorphous silicon may fill in the etched out regions as well as overcoat the patterned P-doped regions. At step 112, a blanket plasma etch is performed, which may etch away the N+ overcoat. At step 114 a lithographic patterning process takes place to define the final pattern of N+ and P+ regions. At step 116, a plasma etch of the backside takes place to pattern and isolate N+ and P+ regions from one another. At step 118, resist is removed. At step 120, the patterned substrate is rinsed, dried, and subjected to an HF clean. At step 122 metal contacts are added to the P+ and N+ regions by screen printing.
As illustrated above, the formation of these types of structures requires at least two lithography steps and an associated set of etch and deposition steps. Because of these steps, the overall throughput and cost of IBC solar cells may be less than ideal for widespread commercial deployment. In view of the above, it will be appreciated that there is a need to improve processing techniques for devices requiring formation of patterned regions that are produced using complex patterning techniques.